The present invention relates to an apparatus and a method of driving an active matrix liquid crystal display (called LCD hereinafter) having a horizontal driver which is capable of reversing pixel signal writing order.
There has been a strong demand for video projectors, flat displays, etc., provided with an active matrix LCD. A video projector is classified into transmission-type and reflection-type. The former type uses a transmission-type LCD as a light valve which modulates light beams per pixel and projects the modulated beams onto a screen. The latter type is provided with a reflecting electrode layer of reflecting pixel electrodes by which light beams are reflected and projected onto a screen.
FIG. 1 shows a conventional active matrix LCD apparatus for reflection-type video projectors. An LCD 31 is provided with MOSFETs 2 arranged in a matrix. The MOSFETs 2 correspond to pixels PX1i to PXnm. Connected to each MOSFET 2 are a charge storage capacitor 3 and a liquid crystal capacitor 25c of a liquid crystal layer. These capacitors are depicted as an equivalent circuit to a liquid crystal displaying device for one pixel.
A gate pulse is supplied from a vertical driver 10 to each gate line 16 to turn on the MOSFETs 2 connected to the gate line. A pixel signal is then supplied from a horizontal driver 15 to the charge storage capacitor 3 connected to each turned-on MOSFET 2.
More in detail, the vertical driver 10 sequentially selects the gate lines in a vertical direction of the matrix to output gate pulses. For each output gate pulse, the horizontal driver 15 supplies pixel signals to horizontally arranged turned-on MOSFETs 2 corresponding to the pixels (PX1i to PXni) to (PX1m to PXnm) to form an image for one field or one frame. Light beams incident to the LCD 31 are modulated per pixel, reflected therefrom and projected onto a screen (not shown).
The horizontal driver 15 is provided with a shift register (not shown) for driving the MOSFETs 2 in a forward or a reverse direction, that is, from the pixel PX1i to PXni or from PXni to PX1i to switch the horizontal scanning direction.
When the LCD 31 is applied to a video projector, a projected image is switched right and left in accordance with a type of the video projector, that is, front projection-type or rear projection-type. The projector is placed in front of a screen in the former type. On the other hand, it is placed behind the screen in the latter type.
Furthermore, when the LCD 31 is applied to a 3-LCD panel liquid crystal displaying device, at least one of images supplied to the three panels is switched right and left in accordance with the mechanism of the optical guidance and synthesizing system installed in the device. Here, the liquid crystal displaying device modulates separated reading light beams for colors of R, G and B on three LCD panels and syntheses the modulated light beams.
The horizontal driver 15 provided with such a shift register for driving the MOSFETs 2 in a forward or a reverse direction as described above however has drawbacks as follows:
Each gate line 16 shown in FIG. 1 has an internal resistor Re and a floating capacitor Ce as shown in FIG. 2A. The floating capacitor Ce exists between the gate line 16 and a silicon substrate for the liquid crystal. Therefore, as shown in FIG. 2B, the internal resistor Re and floating capacitor Ce form a capacitor-resistor (C-R) circuit composed of a capacitor Ct and a resistor Rt between PX1i and PXni.
Suppose that the horizontal driver 15 shown in FIG. 1 is set in the right scanning direction mode in which pixel signals (SIG) are supplied to the LCD 31 in the order of (PX1i.fwdarw.PX2i.fwdarw. . . . .fwdarw.PXni). The pixel signals are shown in FIG. 3A where the pixel signals I (SIG1, SIG2, SIG3, . . . , SIGn) and II (SIG1', SIG2', SIG3', . . . , SIGn') are for the uppermost pixels (PX1i, PX2i, PX3i, . . . PXni) and the next horizontally aligned pixels (not shown), respectively, in FIG. 1.
While a gate pulse is being supplied to the uppermost gate line 16 in FIG. 1 from the vertical driver 10, pixel signals are supplied to the charge storage capacitors 3 via the MOSFETs 2 for the pixels PX1i to PXni in the order mentioned above.
More in detail, the gate pulse shown in FIG. 3B is supplied first to the MOSFET 2 for the leftmost pixel PX1i shown in FIG. 1. The pixel signal SIG1 is also supplied to the MOSFET 2 for the pixel PX1i as shown in FIG. 3C. Also shown in FIG. 3C is the pixel signal SIG1' for the pixel (not shown) next to the pixel PX1i in the vertical direction. The gate pulse is then supplied last as shown in FIG. 3D to the MOSFET 2 for the rightmost pixel PX1n shown in FIG. 1. The pixel signal SIGn is also supplied to the MOSFET 2 for the pixel PX1n as shown in FIG. 3E. Also shown in of FIG. 3E is the pixel signal SIG n' for the pixel (not shown) next to the pixel PX1n in the vertical direction.
The closer to the leftmost pixel PX1i in FIG. 1, the smaller the totals of the resistors Re and capacitors Ce are (FIG. 2A), and the more perfect rectangular waveform the gate pulse has as shown in of FIG. 3B. The MOSFET 2 for the pixel PX1i thus samples and holds the pixel signal SIG1 at the correct timing (S/H timing) when the gate pulse falls as shown in FIGS. 3B and 3C .
On the other hand, the closer to the rightmost pixel PXni, the larger the totals of the resistors Re and capacitors Ce, and the more the gate pulse exhibits decrease in high frequency components at rising and falling moments as shown in FIG. 3D due to the existence of the C-R circuit shown in FIG. 2B.
More in detail, the closer to the rightmost pixel PXni, the more the C-R circuit acts as an integrating circuit with a larger time constant to affect the gate pulse at the rising and falling moments, thus delaying the S/H timing. However, the pixel signal SIGn supplied to the MOSFET 2 for the rightmost pixel PXn1 is also delayed as shown in FIG. 3E in the right scanning direction mode in the order of (PX1i.fwdarw.Px2i.fwdarw. . . . .fwdarw.Pxni). The pixel signal SIGn thus can be supplied to the MOSFET 2 for the pixel PXni even if the S/H timing is delayed. Shown in FIGS. 3D and 3E is the worst case where the S/H timing is delayed most.
Next, suppose that the horizontal driver 15 shown in FIG. 1 is set in the left scanning direction mode in which pixel signals (SIG1, SIG2, SIG3, . . . , SIGn) shown in FIG. 4A are supplied to the LCD panel 31 in the order of (PXni.fwdarw. . . . .fwdarw.Px2i.fwdarw.Px1i), thus switching the image right and left.
For the same reason given with respect to FIGS. 3B and 3C, the closer to the leftmost pixel PX1i in FIG. 1, the smaller the totals of the resistors Re and capacitors Ce are (FIG. 2A), and the more perfect rectangular waveform the gate pulse has as shown in FIG. 4B. The MOSFET 2 for the pixel PX1i thus samples and holds the pixel signal SIGn at the correct S/H timing when the gate pulse falls as shown in FIGS. 4B and 4C.
On the other hand, the closer to the rightmost pixel PXni for which the pixel signal SIG1 is supplied to the corresponding MOSFET 2, the larger the totals of the resistors Re and capacitors Ce are, and the more the gate pulse exhibits decrease in high frequency components at rising and falling moments as shown in FIG. 4D for the same reason given with respect to FIG. 3D.
The MOSFET 2 for the pixel PXni thus erroneously samples and holds the pixel signal SIG1' (not SIG1) at the timing (S/H timing) as shown in FIGS. 4D and 4E. The pixel signal SIG1' should be supplied to the MOSFET 2 (not shown) for the pixel next to the pixel PXni in the vertical direction.
Continuously erroneous sampling and holding at the pixel PXni and other pixels close to PXni due to a large time constant for the C-R circuit shown in FIG. 2B would produce deviation of horizontal scanning lines at the right side of the LCD 31 as shown in FIG. 5.
This deviation would affect an image projected onto a screen, that is, an image of a field or frame next to the present field or frame would be projected at the right side of the screen.